Finally, several important DSP algorithms such as FIR/IIR, FFT and Viterbi decoders are implemented by bit-serial/digit-serial architectures to demonstrate the practical applications of the bit-serial/digit-serial approach. The reasons why the design of programmable processors is not suitable for digit-serial implementation will also be identified. It will be shown that the digit-serial approach favors the design of dedicated architectures. Second, at the same target throughput rate requirement, general qualitative and quantitative comparison between bit-parallel and digit-serial approaches against the programmable and dedicated architectures will be discussed. The proposed arithmetic architectures break the limitation of digit-level pipelining which exists in the conventional architectures, and permit fine-grain level of pipelining which can lead to high throughput rate or very low power consumption. First, the design of high-performance digit-serial arithmetic units including adders, multipliers and complex-number multipliers which form the backbone of the DSP systems will be addressed. This thesis will explore the digit-serial implementation styles from three aspects. Digit-serial systems reduce to bit-serial systems when the digit-size equals one. They promise to be more area and power efficient than the bit-parallel counterparts, and are well suited for moderate sample rate applications. Digit-serial systems process a certain number (digit-size) of bits instead of an entire word as the popular bit-parallel systems do in a single clock cycle. This thesis presents the design of low-power bit-serial and digit-serial DSP systems.
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